Advanced Topic on Reconfigurable FPGA-based Systems Design
2016 Edition
COURSE DESCRIPTION
New application domains demand ever increasing adaptability and performance. In order to cope with changing user requirements, improvements in system features, changing protocol and data-coding standards, and demands for support of a variety of different user applications, many emerging applications in communication, computing and consumer electronics demand that their functionality stays flexible after the system has been manufactured. Reconfigurable Systems-on-a-Chips (SoCs) employing different microprocessor cores and different types of reconfigurable fabrics are one attractive solution for these domains. The increasing prominence of reconfigurable devices within such systems requires HW/SW co-design for SoCs to address the trade-off between software execution and reconfigurable hardware acceleration.
SoC can draw various benefits from such adaptability and efficient acceleration of
compute-intensive tasks. Dynamic reconfiguration capabilities of current reconfigurable devices create an additional dimension in the temporal domain.
During the design space exploration phase, overheads associated with reconfiguration and hardware/software interfacing need to be evaluated carefully in order to harvest the full potential of dynamic reconfiguration.
The course will introduce the student with the concept of reconfigurability in
FPGAs, presenting the available mechanisms and technologies at the device level
and the tools and design methodologies required to design FPGA-based reconfigurable embedded systems. The course will present the different aspects of the design of FPGA-based reconfigurable systems, focusing in particular on dynamically self-reconfigurable systems. The design methodologies and tools
required to design a dynamically-reconfigurable system will be introduced and described, together with the problems that need to be considered. The students
will be introduced to two different approaches to design/program FPGA-based
system: VHDL and HLS. With respect to the HLS scenario the students will have the chance to work with commercial tools like Xilinx Vivado HLS (a C-based tool) and Xilinx SDAcell (an OpenCL-based tool).
NEWS
CLASSES
1. Lecture 1 (@Santa) - 3 Nov, 2016
NECST Meeting Room @ 12pm - 5h
Course introduction - [PPT - V0] or [PDF - V0]
2. Lecture 2 (@Santa) - 9 Nov, 2016
NECST Meeting Room @ 9.30am - 6h
Introduction to FPGA- [PPT - V0] or [PDF - V0]
3. Lecture 3 (@Miele) - 10 Nov, 2016
DEIB Seminar Room @ 9am - 4h
High level synthesis for FPGA: Vivado and Vivado HLS
4. Lecture 4 (@Miele) - 11 Nov, 2016
DEIB Seminar Room @ 9am - 4h
High level synthesis for FPGA: Vivado and Vivado HLS
5. Lecture 5 (@Santa) - 16 Nov, 2016
NECST Meeting Room @ 10am - 2.5h
FPGA: Real Needs and Limits - [PPT - V0] or [PDF -
V0]
6. Lecture 6 (@Santa) - 16 Nov, 2016
NECST Meeting Room @ 1.00pm - 3h
Runtime Support - [PPT - V0] or [PDF -
V0]
7. Lecture 6 (@Miele) - 18 Nov, 2016
DEIB Seminar Room @ 9.30am - 7h
SDAccel and FPGA for HPC:
OpenCL - [PDF - V0]
GPU - [PDF - V0]
8. Lecture 7 - 28 November (@Santa), 2016
NECST Lab Meeting Room, -1 Building 20 @ 9am - 3h
Design Flow - [PPT - V0] or [PDF - V0]
9. Exam - On Demand
NECST Lab Meeting Room, -1 Building 20
Exam: project presentation
READINGS
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