Reconfiguration-Aware Scheduling for FPGA-Based Heterogeneous Architectures

The aim of this project is to show a novel mixed-integer linear programming (MILP) formulation for mapping and scheduling of applications on heterogeneous and reconfigurable devices taking into account partial dynamic reconfiguration (PDR), module reuse and configuration prefetching. Starting from a target architecture and a description of the application in terms of tasks and data dependencies, the proposed formulation allows the designer to optimize a linear combination of different metrics such as execution time, peak power and energy consumption.

The complete description of the MILP model can be found at the following link