Office @ DEIB

Floor: 1, Room: 154
(Not always here) Phone Number: +39.02.2399.4012
(Best choice!) NECSTLab Number: +39.02.2399.3564
Fax Number: +39.02.2399.3411


Marco's CV (Eng)


Google Schoolar
SCOPUS Author ID: 11540913800
ORCID: 0000-0002-9883-9693
Research Gate

Research groups and projects

System Architectures @ Politecnico di Milano
ORCA: Computer Architecture and Operating Systems
DReAMS: Reconfigurable Computing
STeEL: Smart Technologies, Easy Life
FPGA Floorplacer
Tasks Scheduler and Mapper for FPGA-based systems
exaFPGA project
MPower project


Teaching activities

a.a. 22/23 Courses

Creativity, Science and Innovation (Eng) - Polimi - Second Semester, Prof. Aldo Torrebruno, and Prof. Marco D. Santambrogio (Course webpage)
Advanced Computer Architectures (Eng) - Second Semester, Prof. Marco D. Santambrogio (Course webpage)
High Performance and Processors and Systems (Eng) - Second Semester, Prof. Marco D. Santambrogio (Course webpage)
Corso di Fondamenti di Informatica (It) - Polimi - Second Semester, Prof. Marco D. Santambrogio (Course webpage)

Polimi: Politecnico di Milano, Milano, Italy.
UIC: University of Illinois at Chicago, Chicago, Illinois - USA

The complete list of all my teaching activities is available at this [link].


Postdoc Fellow, Massachusetts Institute of Technology, MA, USA;
Ph.D. degree in Information Engineering, Politecnico di Milano, Italy;
Master degree in Computer Science, University of Illinois at Chicago, Chicago, USA;
Laurea in Computer Engineering, Politecnico di Milano, Italy.


Progetto Rocca Post-doc Fellowship

December, 2008 - he has been awarded a Progetto Rocca Post-doc Fellowship.

Dimitri N. Chorafas PhD Thesis Award

From the Chorafas Foundation (Berne, Switzerland) for the best PhD Theses in Systems Engineering and Information Technology May 2008. Thesis title: Hardware/Software codesign methodologies for dynamically reconfigurable systems.

Best paper award

15th International Conference on Very Large Scale Integration, IFIP VLSI-SoC 2007, ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching.

Co-author of the Best Student Paper award

7th IEEE International Conference on Autonomic Computing (ICAC) 2010, Smartlocks: Lock Acquisition Scheduling for Self-Aware Synchronization.

Research Grants

HiPEAC Collaboration Grant

Title of the research: Self-Aware Reconfigurable Computing Systems for Energy Saving and Performance Enhancement, November 2010 - December 2011

HiPEAC Collaboration Grant

Title of the research: Self-aware and autonomic system, July 2009

Swiss NSF Research Project (Division II).

Titleof the project: Dynamically Adaptive Architectures for Nomadic Embedded Systems. PDF proving the participation

Industrial Partner

Maxeler Technologies
Maxeler University Program MAX-UP
Maxeler Technologies

EU Projects


To handle the stringent performance requirements of future exascale High Performance Computing (HPC) applications, HPC systems will need ultra-efficient heterogeneous compute nodes. Some of these nodes will be high performance CPU nodes but other nodes will have to be targeted to specific applications and maximally exploit low-level parallelism. At the same time, these specific hardware nodes will need to be flexible enough to adapt to different application requirements as it is infeasible to include specific nodes for all possible applications that run on the HPC system. Reconfigurability of these hardware nodes is therefore required and, for applications that significantly change their behaviour during their execution, run-time reconfiguration will be an important asset of such hardware nodes. In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures and tools with run-time reconfiguration built-in from the start. The idea is to enable the joint optimization of architecture, tools, applications, and reconfiguration technology in order to prepare for the necessary HPC hardware nodes of the future. The main objective of the EXTRA project is therefore to develop an open source research platform for continued research on reconfiguration architectures and tools. The goal is to find architectures and tools that match the next-generation HPC application requirementse. We want to provide the European platform for run-time reconfiguration that will enable increased research efforts on run-time reconfiguration in Europe.


The SAVE project (Self-Adaptive Virtualisation-aware high-performance/low-Energy heterogeneous system architectures) aims at exploiting self-adaptivity and hardware-assisted virtualisation to allow the system to autonomously decide which specialised computing resources are exploited to achieve a more efficient execution based on user-defined optimisation goals, such as performance, energy, reliability. SAVE will define crosscutting SW/HW technologies for implementing self-adaptive systems exploiting GPUs and FPGA-based dataflow engines (DFEs) that enhance heterogeneous architectures to cope with the increased variety and dynamics of high-performance and embedded computing workloads. Virtualisation and self-adaptation are jointly exploited to obtain a new self-adaptive virtualisation-aware Heterogeneous System Architecture (saveHSA). This architecture exhibits a highly dynamic behaviour to achieve the requested performance while minimising energy consumption allocating tasks to the most appropriate computing resources. This objective is supported by two main technologies: i) novel runtime OS components to manage the HSA by migrating the computation from one resource to another, and ii) hardware-assisted virtualisation support for GPUs and DFEs.
Official website:


FASTER will facilitate the use of reconfigurable technology by providing a complete methodology that enables designers to easily implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology. We expect that the project will lead to a 20% productivity improvement due to seamless implementation and verification of dynamically changing systems, a 50% total ownership cost reduction for NIDS and Reverse Time Migration systems, with a 2x performance improvement under power constraints for Global Illumination and Image Analysis.
Official website:
PDF proving the participation as WP2 leader

Research Areas

Computer Architectures && Embedded system design;
Dynamic reconfiguration in embedded system - [DRESD website];
Operating Systems - [CHANGE website];
HW/SW Codesign;
Combinatorial Optimization.

Research Interests

The research interests cover mainly the computer architecture and design automation areas:

Self-adaptable and autonomic systems

A self-adaptive and autonomic computing system is a system able to configure, heal, optimize and protect itself without the need for human intervention. Therefore, aim of this research is to develop performance models and prototypes of software and hardware components required to support the operating system and enable the same application to achieve its goals while working on different systems.

Research && Education

how to create a win-win game where research and the students experience are positively influenced one other.

Methodologies for dynamic reconfiguration in embedded system

Aim of this research is the definition of methodologies and tools for implementing dynamic reconfigurable systems, through the exploration of the solution space, in order to evaluate the most effective solutions that are compatible with the design constraints.

Operating System support for reconfigurable computing

Develop an operating system, for FPGA-based architecture, able to determine where a module should be configured, and to provide an interface towards the final user in order to request a hardware application in a simplified way. The operating system has to be able to manage on-demand module configuration on an FPGA while providing a set of high-level abstractions to user applications.

Methodologies for hardware/software co-design of embedded systems

Aim of this research work is the development of a methodology and a set of tools for capturing specifications of control-dominated systems, design space exploration, hardware/software partitioning, co-synthesis and co-simulation.


Graphics by Federico Nava: navafederico AT gmail DOT com